@MZ_Grundschrift:SLVS-EC v3.0 Rx IP is an interface IP core conceived to run on multiple FPGAs. Using this IP, users can implement products that support the latest SLVS-EC standard v3.0. Macnica ATD Europe has also created an evaluation platform with the tools needed to start developments. The FPGA can receive signals directly from the SLVS-EC Interface. It supports De-Skew functionand enables board design without considering skew that occurs between lanes. Hall 8 | Booth D30